Standards-compliant IP for on-board compression, and FPGA design & verification services for the imaging and aerospace industry.
A JPEG-LS encoder IP core for FPGAs — real-time, lossless image compression at a fraction of the computational cost of JPEG 2000 lossless, with no external memory. Single-component, one pixel per clock, and vendor-agnostic, so it targets any platform and scales across sensor bands.
Conformance is proven byte-exact against CharLS, an independent open-source implementation of ISO/IEC 14495-1. It is dual-licensed — free under GPL v3, with a commercial license for proprietary products.
Full specifications, architecture & verification →We take hardware from requirement to verified netlist.
Vendor-agnostic RTL architecture and implementation — pipelines, streaming datapaths, and control planes built for real-time throughput and portability across Xilinx, Intel, Lattice and Microchip parts.
Constrained-random, coverage-driven verification in OSVVM, with independent golden models and embedded assertions, at RTL and post-synthesis netlist — then hardware-in-the-loop on a real device, so the last check is silicon rather than simulation.
On-board compression, sensor interfacing and pixel pipelines for multi-band and high-resolution imagers.
Space-grade design practices for MPSoC platforms common in flight systems — deterministic behavior, resource-lean logic, and verification evidence you can put in front of a review board.