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OpenJLS

A JPEG-LS encoder IP core for FPGAs — real-time lossless image compression.

VHDL-93 ISO/IEC 14495-1 Vendor-agnostic v1.1

OpenJLS implements the JPEG-LS standard — a low-complexity lossless image codec with compression ratios comparable to JPEG 2000 lossless, at a fraction of the computational cost and with no external memory required. It reaches roughly 240 MHz on a Xilinx UltraScale+ ZU7EG, an MPSoC common in space applications, and processes one pixel per clock. The whole project is open source — the RTL, the testbenches and the verification flow are all public.

It handles single-component (grayscale) data, so a multi-band sensor uses one compressor per band — resource usage is low enough to run every band in parallel. The core is vendor-agnostic, targeting any FPGA platform, and builds with Vivado, Quartus, Libero, Lattice or open-source tools.

01 · Specifications


CompressionLossless JPEG-LS
Compression ratio~1.5 : 1 expected, Earth imaging
Pixel depth8–16 bits
ComponentsGrayscale, single
Image sizeUp to 64k × 64k pixels
MemoryOn-chip line buffer
Throughput1 pixel / clock
InterfaceReady/valid, or AXI4-Stream + AXI4-Lite
ConformanceByte-exact vs. CharLS
PortabilityVendor-agnostic VHDL

Ratio is data-dependent: the core is byte-exact, so output size follows the entropy of your imagery, not a quality setting. Lossless still-image coding generally lands between 1.5 : 1 and 2.5 : 1. Our own measurement — 1.63 : 1 — is the average over a 287-image mixed test corpus.

02 · Architecture


OpenJLS follows the JPEG-LS encoding pipeline, implemented as a fully pipelined, vendor-agnostic VHDL core.

01

Gradient computation

Local gradients from causal pixel neighbors.

02

Context modeling

365 contexts with adaptive bias correction.

03

Prediction

MED predictor with context-based bias cancellation.

04

Encoding

Adaptive Golomb-Rice, with run-length for uniform regions.

05

Bitstream packing

ISO/IEC 14495-1 compliant JPEG-LS output.

03 · Resources & performance


A single generic sets both cost and speed: MAX_IMAGE_WIDTH sizes the on-chip line buffer. Logic stays flat as it grows — only Block RAM follows — and the best implementation strategy holds frequency in a narrow band across the whole range.

Max frequency ~241–253 MHz
LUTs ~7,600
Flip-flops ~2,100
Device Zynq UltraScale+ ZU7EG
0 2k 4k 6k 8k 0 8 16 24 32 4k 8k 12k 16k 32k 64k Maximum image width — pixels LUT / FF Block RAM tiles LUTs Flip-flops Block RAM
Fig. 01 — Resource usage vs. maximum image width
180 200 220 240 260 4k 8k 12k 16k 32k 64k Maximum image width — pixels Maximum frequency — MHz Best of four strategies Default strategy Spread across strategies
Fig. 02 — Maximum frequency vs. maximum image width

Both figures characterized on a Zynq UltraScale+ xczu7eg-fbvb900-1-e (speed grade −1, slowest), Vivado 2025.2, 12-bit grayscale. Frequencies are true fmax — read by over-constraining the clock until the design failed timing. Resource figures use the default strategy; utilization is near-identical across strategies. RTL only, no floorplanning or vendor-specific optimization: representative, not guaranteed.

04 · Verification


Verified at three levels. In simulation, a layered suite — constrained-random self-checking tests, functional coverage, and byte-exact comparison against CharLS, an independent open-source implementation of JPEG-LS — runs at both RTL and post-synthesis gate level. The same corpus is then re-encoded on a real device: the core runs on a PYNQ-Z2 and the returned bitstreams are compared byte-for-byte against the same reference.

Golden model287/287 byte-exact
OSVVM suite139,393 affirmations
Code coverage99.8% statements
In hardware287/287 byte-exact on PYNQ-Z2
Live verification report →

05 · Licensing


GPL v3

Free for any use that complies with GPL v3. Evaluation is unrestricted — clone, simulate, synthesize and test freely.

Commercial

For proprietary, closed-source products without GPL obligations. A commercial license is only required when shipping a product.

Inquire about licensing Datasheet (PDF) View on GitHub