Projects

A record of what we have proven in hardware.

Work taken from requirement to verified hardware.

01 · 2026

Host workstation rear I/O with the Ethernet link active — Fig. 01 — Hardware-in-the-loop bench: host to PYNQ-Z2 over Ethernet

PYNQ-Z2 board powered up, Ethernet and USB attached — Fig. 01 — Hardware-in-the-loop bench: host to PYNQ-Z2 over Ethernet

Encode Over Ethernet Hardware verification PYNQ-Z2

Encode over Ethernet

The hardware tier of OpenJLS verification, and the one simulation cannot stand in for. An image goes in over Ethernet and its compressed .jls file comes back — the encoder exercised end to end on a real device rather than in a testbench.

Verified in hardware across the full corpus of 287 images spanning every supported pixel depth: the FPGA output is byte-exact against the CharLS reference. The 581 MB corpus comes back losslessly compressed to 356 MB. The whole hardware-in-the-loop sweep is reproducible from a clean clone.

View the demo on GitHub →

Corpus: 287 images
Depths: 8–16 bits
Result: Byte-exact
Compression (corpus avg.): 1.63 : 1

02 · Next

More projects in progress

New demonstrations and case studies are added here as they are verified in hardware.