FPGA design & IP cores for aerospace and imaging.

High-technology hardware, built to specification and proven in silicon.

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Isentropic designs FPGA hardware for imaging and aerospace — where an image is captured once and cannot be retaken.

We prefer correctness to cleverness. Every design is measured against an independent reference and verified before it ships.

What we do

FPGA design

RTL architecture and implementation for real-time imaging and space-grade systems, portable across vendors.

Verification

Coverage-driven suites checked byte-exact against independent references — at RTL, at gate level, and in hardware.

IP cores

Licensable, standards-compliant cores such as the OpenJLS JPEG-LS encoder.

Technical work

Built in hardware. Proven against the standard.

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OpenJLS — JPEG-LS encoder IP core v1.1 ISO/IEC 14495-1

A vendor-agnostic JPEG-LS encoder for FPGAs — low-complexity lossless image compression. Built for real-time on-board imaging where resources and power are scarce. Verified byte-exact across a 287-image corpus.

Read the specifications →
Throughput
~240 Mpixel/s
Image size
Up to 64k × 64k pixels
Bit depth
8–16 bits
Targets
Vendor-agnostic
Encode Over Ethernet — hardware demo PYNQ-Z2 Byte-exact

A full hardware-in-the-loop demo for OpenJLS: raw images stream to a board over Ethernet, are encoded inside the FPGA, and the .jls files stream back. Validated against CharLS, an independent open-source C++ implementation of JPEG-LS.

See the project →
Corpus
287 images
Result
Byte-exact
Reference
CharLS
Compression (corpus avg.)
1.63 : 1